The term “hysteresis” generally refers to the process of compensating for variations (e.g., “noise”) in an input signal by adjusting the point at which a system reacts to the input signal. For example, in electrical circuits a rising signal can be detected at a first and higher voltage level (the “rising edge trip point”), while a falling signal can be detected at a second and lower voltage level (the “falling edge trip point”). FIGS. 1–3 are waveform diagrams that can be used to describe this type of hysteresis, which is referred to herein as “level hysteresis”.
FIG. 1 illustrates the process of an ideally clean input signal IN rising and falling, and its effect on an output signal OUT of inverter 101. Input signal IN rises linearly from a low value (e.g., a ground value) to a high value (e.g., power high VDD). Half-way through the rising edge, at time Tr, the voltage level on signal IN reaches the trip point tp and inverter 101 is triggered. Thus, the output signal OUT from inverter 101 begins to fall. Signal OUT also falls linearly in this ideal circuit, from the high value to the low value. After a time, input signal IN changes state again, falling linearly from the high value to the low value. Half-way through the falling edge, at time Tf, the voltage level on signal IN reaches the trip point tp and inverter 101 is triggered. Thus, the output signal OUT from inverter 101 begins to rise. Signal OUT also rises linearly in this ideal circuit, from the low value to the high value. Thus, signal OUT is a noise-free output signal ideally suited to drive other circuitry.
FIG. 2 illustrates what happens to the idealized signals of FIG. 1 in a noisy signal environment. Both the rising and falling edges of signal IN are subject to sudden alterations that can momentarily cause the signal to rise above, then fall below, the trip point tp. Each time input signal IN rises above the trip point (e.g., at times T1, T3, and T5), output signal OUT changes from the high value to the low value. Each time input signal IN falls below the trip point (e.g., at times T2, T4, and T6), output signal OUT changes from the low value to the high value. The result is a noisy output signal OUT, as shown in FIG. 2.
FIG. 3 illustrates the resulting waveforms when inverter 101 is replaced by a Schmitt trigger 301. Schmitt triggers are well known. For example, one Schmitt trigger is described by Hsieh in U.S. Reissue Patent No. Re. 34,808, “TTL/CMOS Compatible Input Buffer with Schmitt Trigger”, which is incorporated herein by reference. A Schmitt trigger provides level hysteresis in the manner previously described, by providing different trip points for the rising and falling edges of the input signal. The rising edge trip point tpr is higher than the falling edge trip point tpf. Thus, the brief and limited negative movements in voltage level during the rising edge of input signal IN do not cause the output signal OUT to rise to the high value. Similarly, the brief and limited positive movements in voltage level during the falling edge of input signal IN do not cause the output signal OUT to fall to the low value. Hence, the circuit of FIG. 3 is noise-immune, provided the extent of the noise does not exceed the protection provided by the difference in trip-points.
Schmitt triggers can be very useful, when they are available. However, they do have their drawbacks in some applications. For example, Schmitt triggers are analog circuits that cannot readily be implemented in the digital programmable logic generally available in programmable logic devices (PLDs). PLDs typically provide arrays of digital logic elements that can be programmed to assume various configurations performing desired digital functions. However, analog functions typically cannot be implemented in a PLD unless they are deliberately included in the fabric of the PLD by the PLD designer and manufacturer.
Therefore, it is desirable to provide digital circuits and methods of providing hysteresis, e.g., hysteresis circuits and methods that can be implemented in digital PLDs.